What Is WAT Test? Complete Guide to Wafer Acceptance Test in Semiconductor Manufacturing

Wafer Acceptance Test (WAT), sometimes called Electrical Wafer Sort (EWS), is one of the most critical processes in semiconductor manufacturing. It ensures that each processed wafer meets electrical performance standards before it proceeds to assembly, packaging, and final test. Because WAT captures process variations early, it plays a central role in yield control, process tuning, and reliability improvement.

This article provides a comprehensive, expert-level explanation of WAT test, including definitions, test structures, typical measurements, common problems, and how modern fabs use WAT data for high-precision process monitoring.

1. What Is WAT Test?

WAT Test = Wafer Acceptance Test
It is performed after wafer fabrication but before dicing and packaging, using a parametric analyzer + probe station to measure electrical characteristics of embedded test structures.

• Validate whether the wafer meets process specifications

• Detect process drifts or failures early

• Provide feedback to lithography, etch, deposition, CMP, and diffusion processes

• Predict final yield and reliability

• Identify wafer-level or lot-level abnormalities

WAT is not functional testing of chips—it focuses on process parameters, not device operation.

2. Why WAT Testing Matters

Packaging is the most expensive step. Detecting failed wafers early reduces cost dramatically.

Foundries adjust lithography focus, etch rate, or implant dose based on WAT data.

Critical circuits (SRAM, analog blocks, RF modules) rely on consistent transistor parameters.

WAT signatures often correlate with yield loss patterns.

Parameters like Vt mismatch or gate leakage strongly influence long-term device reliability.

3. What Equipment Is Used in WAT?

WAT requires extreme measurement accuracy, especially for sub-nanometer and FinFET nodes.

4. What Gets Measured in WAT? (Typical Test Structures)

Modern wafers include thousands of on-die test structures. These fall into several categories:

4.1 Transistor-Level Measurements

• ・ Threshold Voltage (Vt)

• ・ Id-Vg / Id-Vd curves

• ・ Leakage Current (Ioff)

• ・ Drive Current (Ion)

4.2 Interconnect and Metal Measurements

• ・ Contact resistance (Rc)

• ・ Line resistance (Rmetal)

• ・ Via chain resistance

• ・ Metal sheet resistance (Rs)

4.3 Passive Component Tests

• ・ Poly resistor

• ・ MIM capacitor

• ・ Inductor Q-factor (RF processes)

4.4 Dielectric Integrity

• ・ Gate oxide breakdown (BVG)

• ・ Leakage current (Igate)

• ・ TDDB-related test structures

4.5 Linewidth & Overlay Related Electrical Tests

• ・ CD (critical dimension) variation measured electrically

• ・ Lithography focus/exposure derived from WAT

5. WAT Test Flow (Step-by-Step)

Below is a simplified yet realistic WAT workflow used in fabs:

Each wafer has a predefined test map aligned to the process design kit (PDK).

Needles must contact micro-pads, usually 60–100 μm in size.

Using an analyzer with SMUs, CCUs, and high-accuracy modules.

All parametric results uploaded to MES and APC servers.

Engineers check:

• ・ Mean

• ・ Standard deviation

• ・ Cp/Cpk

• ・ Trend charts

• ・ Drift analysis

• ・ PASS: Wafer goes to dicing

• ・ FAIL: Hold, rework, or scrap

Abnormalities feed back to lithography, deposition, implant, etc.

6. What Parameters Are Most Important in WAT?

Different fabs focus on different parameters depending on node and device type. However, the following are universally critical.

• ・ Foundation of transistor behavior

• ・ Sensitive to implant dose, anneal, and oxide thickness

• ・ Evaluates dopant activation and uniformity

• ・ Key factor for high-speed logic

• ・ Indicates issues in etch, liner deposition, and CMP

Excess leakage indicates:

• ・ Gate oxide defects

• ・ Junction leakage

• ・ Contamination

• ・ Line resistance

• ・ Via chain yields

7. Common WAT Fail Modes

8. How Fabs Use WAT Data (Advanced Applications)

8.1 APC (Advanced Process Control)

Real-time tuning:

• ・ Litho focus/exposure compensation

• ・ Implant dose auto-adjustment

• ・ CMP endpoint prediction

8.2 Yield Prediction Models

Machine learning models correlate WAT signatures with:

• ・ SRAM Vmin

• ・ Analog matching variation

• ・ Logic yield patterns

8.3 Reliability Forecasting

WAT directly influences:

• ・ TDDB (Time-Dependent Dielectric Breakdown) predictions

• ・ EM (Electromigration) modeling

• ・ HCI (Hot Carrier Injection) behavior

9. How WAT Differs from Other Tests

WAT is bridge between inline metrology and functional chip probe.

Conclusion

WAT (Wafer Acceptance Test) is the most critical electrical parametric test in wafer fabrication. It ensures process quality, reduces downstream failures, and provides essential data for inline control and yield engineering. With the increasing complexity of semiconductor devices, WAT continues to be the backbone of process monitoring in advanced fabs.

If you need guidance on probe stations, parametric analyzers, probe cards, or WAT test setup, feel free to reach out—our technical team can provide professional assistance.